Novel approaches to the design of VLSI RNS multipliers

DOI10.1109/82.204109zbMath0776.11072OpenAlexW2113415079MaRDI QIDQ4005155

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Publication date: 27 September 1992

Published in: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/82.204109

zbMATH Keywords

multiplicationresidue number systemGalois fieldVLSI algorithmindex group

Mathematics Subject Classification ID

Circuits, networks (94C99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Congruences; primitive roots; residue systems (11A07) Computational number theory (11Y99)

Related Items (3)

Efficient hardware implementation of finite fields with applications to cryptography ⋮ How to fake an RSA signature by encoding modular root finding as a SAT problem ⋮ Arithmetic division in RNS using Galois field \(GF(p)\)

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