Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach

DOI10.1016/0167-9260(92)90025-TzbMath0758.94022MaRDI QIDQ4015507

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Publication date: 13 January 1993

Published in: Integration (Search for Journal in Brave)

zbMATH Keywords

complexitycombinatorial optimizationVLSI designheuristic algorithmsconsecutive ones propertygate matrix layoutPLA foldingmatrix layout problem

Mathematics Subject Classification ID

Combinatorial optimization (90C27) Applications of graph theory to circuits and networks (94C15)

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