An Algorithm for the Generation of Test Sets for Combinational Logic Networks

DOI10.1109/T-C.1975.224295MaRDI QIDQ4132415zbMATH OpenFDO

Authors David T. Wang

Publication date 1975

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/T-C.1975.224295

Mathematics Subject Classification ID

Cited in

(3)

• An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits
• Electronic circuit diagnostic expert systems - a survey
• A complete critical path algorithm for test generation of combinational circuits

This page was built for publication: An Algorithm for the Generation of Test Sets for Combinational Logic Networks

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4132415)