A Compact High-Speed Parallel Multiplication Scheme

DOI10.1109/TC.1977.1674730zbMATH Open0368.94037OpenAlexW2112637319MaRDI QIDQ4145290FDOQ4145290

Authors: William J. Stenzel, William J. Kubitz, Gilles H. Garcia 

Publication date: 1977

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1977.1674730

Mathematics Subject Classification ID

Formal languages and automata (68Q45)

Cited In (2)

• A class of systolic multiplier units for VLSI technology
• Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

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