Some improved designs for the digital summation threshold logic (DSTL) gate

DOI10.1093/COMJNL/21.1.73zbMATH Open0368.94039OpenAlexW2034784819MaRDI QIDQ4145292FDOQ4145292

C. R. Edwards

Publication date: 1978

Published in: The Computer Journal (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1093/comjnl/21.1.73

Mathematics Subject Classification ID

This page was built for publication: Some improved designs for the digital summation threshold logic (DSTL) gate

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4145292)