Analysis of speed of a binary divider using a variable number of shifts per cycle

DOI10.1093/COMJNL/21.3.246zbMATH Open0385.94032OpenAlexW4231441239MaRDI QIDQ4166705FDOQ4166705

Keith H. Bennett, M. Patel

Publication date: 1978

Published in: The Computer Journal (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1093/comjnl/21.3.246

Mathematics Subject Classification ID

Circuits, networks (94C99) Theory of software (68N99)

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