Use of minimum-adder multiplier blocks in FIR digital filters

DOI10.1109/82.466647zbMATH Open0943.68501OpenAlexW2103244632MaRDI QIDQ4338087FDOQ4338087

Authors: Andrew G. Dempster, Malcolm D. Macleod 

Publication date: 7 August 1997

Published in: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/82.466647

Mathematics Subject Classification ID

Computer system organization (68M99)

Cited In (4)

• Fast discrete Fourier transform computations using the reduced adder graph technique
• Algebraic methods for optimizing constant multiplications in linear systems
• Optimization of linear phase FIR filters in dynamically expanding subexpression space
• Reconfigurable multiplier blocks: Structures, algorithm and applications

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