The QC-2 parallel queue processor architecture

DOI10.1016/J.JPDC.2007.08.004zbMATH Open1243.68092OpenAlexW2125133818MaRDI QIDQ436683FDOQ436683

Authors: Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa 

Publication date: 26 July 2012

Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jpdc.2007.08.004

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zbMATH Keywords

designparallelcircular queue-registerqueue computingqueue processor

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Distributed systems (68M14)

Cites Work

• Stack and Queue Layouts of Directed Acyclic Graphs: Part I
• A SIGNED BINARY MULTIPLICATION TECHNIQUE

Cited In (3)

• Title not available (Why is that?)
• A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems
• Equivalent single-queue-single-server model for a pentium processor

Uses Software

• MiBench
• MediaBench

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