Practical delay enforced multistream (DEMUS) control of deeply pipelined processors

DOI10.1109/12.372038MaRDI QIDQ4419670zbMATH OpenOpenAlexFDO

Authors Daniel C. McCrackin

Publication date 1995

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.372038

zbMATH Keywords

multithreaded computerssimulated performance

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Recommendations

• Delay-insensitive pipelined communication on parallel buses
• Delay-insensitive gate-level pipelining
• Delay composition in preemptive and non-preemptive real-time pipelines
• The minimal average latency of multiconfigurable pipelines

Cited in

(3)

• Models for control unit synchronization on shared control architectures
• Multithreaded Processors
• DMAC: Deadline-Miss-Aware Control

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