Practical delay enforced multistream (DEMUS) control of deeply pipelined processors

DOI10.1109/12.372038zbMATH Open1040.68531OpenAlexW2092174724MaRDI QIDQ4419670FDOQ4419670

Authors: Daniel C. McCrackin 

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.372038

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zbMATH Keywords

multithreaded computerssimulated performance

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Cited In (2)

• DMAC: Deadline-Miss-Aware Control
• Multithreaded Processors

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