Fast combinatorial RNS processors for DSP applications

DOI10.1109/12.381948zbMath1041.68502OpenAlexW2117919933MaRDI QIDQ4419693

Elio D. Di Claudio, Gianni Orlandi, Francesco Dalla Piazza

Publication date: 1995

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.381948

zbMATH Keywords

VLSI processorsbinary multipliers

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

Related Items (4)

RNS architectures for the implementation of the `diagonal function' ⋮ Efficient hardware implementation of finite fields with applications to cryptography ⋮ Enhancing Mersenne transforms by RNS with application to discrete convolution ⋮ Arithmetic division in RNS using Galois field \(GF(p)\)

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