Memory latency effects in decoupled architectures

DOI10.1109/12.324539MaRDI QIDQ4419782zbMATH OpenOpenAlexWikidataFDO

Authors Lizy Kurian, Paul T. Hulina, Lee D. Coraor

Publication date 1994

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.324539

zbMATH Keywords

simulationperformance analysiscache memoriespipelined computers

Mathematics Subject Classification ID

Computer system organization (68M99)

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Cited in

(2)

• Performance evaluation of a decoded instruction cache for variable instruction length computers
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