Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry

DOI10.1109/12.537126MaRDI QIDQ4420848zbMATH OpenOpenAlexFDO

Authors Daniel H. Linder, James C. Harden

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://semanticscholar.org/paper/074411af7e59ae11a9d27937750fe542d5f2cd50

zbMATH Keywords

asynchronous circuitryLevel-Encoded two-phase Dual-Rail

Mathematics Subject Classification ID

Computer system organization (68M99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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