A dual precision IEEE floating-point multiplier

DOI10.1016/S0167-9260(00)00006-7zbMATH Open0952.68164OpenAlexW2161071506MaRDI QIDQ4520152FDOQ4520152

Authors:

Publication date: 12 December 2000

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0167-9260(00)00006-7

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zbMATH Keywords

roundingfloating point multiplierIEEE floating point arithmetic

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (3)

• Binary Integer Decimal-Based Floating-Point Multiplication
• On the design of IEEE compliant floating point units
• Low-energy instruction precision assignment for multi-mode multiplier under accuracy and performance constraints

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