Feasibility analysis for robustness quantification by symbolic model checking

DOI10.1007/S10703-011-0121-5zbMATH Open1247.68156OpenAlexW2087761502MaRDI QIDQ453480FDOQ453480

Authors: Souheib Baarir, Cécile Braunstein, Emmanuelle Encrenaz, J.-M. Ilié, Isabelle Mounier, Denis Poitrenaud, Sana Younes 

Publication date: 27 September 2012

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10703-011-0121-5

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zbMATH Keywords

bounded model checkingcircuit robustness evaluationdependability analysissoft errorssymbolic model checking

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Fault detection; testing in circuits and networks (94C12)

Cites Work

• Self-stabilization
• Self-stabilizing systems in spite of distributed control
• Automatic verification of finite-state concurrent systems using temporal logic specifications
• Title not available (Why is that?)
• Title not available (Why is that?)

Cited In (4)

• Not all bugs are created equal, but robust reachability can tell the difference
• Towards robustness analysis using PVS
• Title not available (Why is that?)
• Formal Analysis of Robustness at Model and Code Level

Uses Software

• sharpSAT

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