Scheduling memory accesses through a shared bus

DOI10.1016/S0166-5316(01)00050-5MaRDI QIDQ4538464zbMATH OpenOpenAlexFDO

Authors E. Almog, Hadas Shachnai

Publication date 14 July 2002

Published in Performance Evaluation (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0166-5316(01)00050-5

zbMATH Keywords

bus architecture

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

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(2)

• Buffered banks in multiprocessor systems
• Distributed order scheduling and its application to multi-core DRAM controllers

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