Hierarchical fault diagnosis of analog integrated circuits

DOI10.1109/81.940182MaRDI QIDQ4540168zbMATH OpenOpenAlexFDO

Authors Chung Kin Ho, P. Shepherd, Friedman Eberhardt, W. Tenten

Publication date 21 July 2002

Published in IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/81.940182

zbMATH Keywords

analog integrated circuitsdiagnosis algorithmfault diagnosisfault locationhierarchical systemsintegrated circuit testinglarge scale circuits

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Fault detection; testing in circuits and networks (94C12) Applications of graph theory to circuits and networks (94C15)

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Cited in

(12)

• Functional fault models for analog circuit elements
• Fast algorithms for selection of test nodes of an analog circuits using a generalized fault dictionary approach
• Application of extension neural network type-1 to fault diagnosis of electronic circuits
• A unified decomposition approach for fault location in large analog circuits
• Design of testability for analogue fault diagnosis
• A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits
• Design of mixed-signal systems for testability
• Frequency-domain grouping robust fault diagnosis for analog circuits with uncertainties
• scientific article; zbMATH DE number 2065120 (Why is no real title available?)
• A classical parameter identification method and a modern test generation algorithm
• Diagnosability of analog circuits packaged as multielement two-terminal branches
• Functional design errors in digital circuits. Diagnosis correction and repair

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