COMPUTATION TIME AND IDLE TIME OF TILING TRANSFORMATION ON A NETWORK OF WORKSTATIONS

DOI10.1142/S0129053300000126zbMATH Open1005.68010MaRDI QIDQ4550159FDOQ4550159

Authors: Shailesh R. Sathe, P. M. Nawghare 

Publication date: 4 March 2003

Published in: International Journal of High Speed Computing (Search for Journal in Brave)

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zbMATH Keywords

tilingidle timenetwork of workstations

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

Cited In (2)

• A pipelined schedule to minimize completion time for loop tiling with computation and communication overlapping
• Title not available (Why is that?)

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