scientific article; zbMATH DE number 1798189
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Publication:4553262
zbMATH Open0996.68578MaRDI QIDQ4553262FDOQ4553262
Authors: Per Bjesse, Tim Leonard, Abdel Mokkedem
Publication date: 4 November 2002
Title of this publication is not available (Why is that?)
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Computing methodologies and applications (68U99) Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)
Cited In (19)
- Backdoors to q-Horn
- The state of SAT
- A taxonomy of exact methods for partial Max-SAT
- Scalable error detection using Boolean satisfiability
- Quantifier reordering for QBF
- Design and results of the first satisfiability modulo theories competition (SMT-COMP 2005)
- Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors.
- An automata-theoretic approach to infinite-state systems
- A formal methods approach to predicting new features of the eukaryotic vesicle traffic system
- Backdoors to satisfaction
- Benchmarking a model checker for algorithmic improvements and tuning for performance
- Unrestricted vs restricted cut in a tableau method for Boolean circuits
- A semantic condition for data independence and applications in hardware verification
- Soundness of \(\mathcal{Q}\)-resolution with dependency schemes
- SCIP: solving constraint integer programs
- A transformation-based approach to implication of GSTE assertion graphs
- 3-Valued Circuit SAT for STE with Automatic Refinement
- SAT-solving in practice, with a tutorial example from supervisory control
- Complete Boolean satisfiability solving algorithms based on local search
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