High-speed and reduced-area modular adder structures for RNS

DOI10.1109/12.980018zbMath1392.68047OpenAlexW2140867083MaRDI QIDQ4571314

Ahmad A. Hiasat

Publication date: 9 July 2018

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.980018

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

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A new high dynamic range moduli set with efficient reverse converter ⋮ Core function of an RNS number with no ambiguity

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