An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes

DOI10.1109/TCSI.2007.902611zbMATH Open1374.68021MaRDI QIDQ4590264FDOQ4590264

Authors: Bane Vasić, Shashi Kiran Chilappagari 

Publication date: 20 November 2017

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Linear codes (general theory) (94B05) Mathematical problems of computer architecture (68M07)

Cited In (1)

• Nanowire addressing with randomized-contact decoders

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