Circuit Size Lower Bounds and #SAT Upper Bounds Through a General Framework

DOI10.4230/LIPIcs.MFCS.2016.45zbMath1398.68193OpenAlexW2542610836MaRDI QIDQ4608607

Suguru Tamaki, Alexander Golovnev, Alexander S. Kulikov, Alexander V. Smal

Publication date: 21 March 2018

Full work available at URL: http://drops.dagstuhl.de/opus/volltexte/2016/6458/

zbMATH Keywords

lower boundssatisfiabilitycircuit complexityexponential time algorithms

Mathematics Subject Classification ID

Related Items (4)

On the limits of gate elimination ⋮ Unnamed Item ⋮ On the complexity of unique circuit SAT ⋮ Gate elimination: circuit size lower bounds and \#SAT upper bounds

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