High level synthesis of synchronous parallel controllers

DOI10.1007/3-540-61363-3_6zbMath1418.68133OpenAlexW1577611457MaRDI QIDQ4633158

Erik L. Dagless, Krzysztof Biliński

Publication date: 2 May 2019

Published in: Application and Theory of Petri Nets 1996 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/3-540-61363-3_6

zbMATH Keywords

high-level synthesisBoolean functionbinary decision diagramfinite state machinestate assignment

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Mathematical problems of computer architecture (68M07)

Cites Work

• Verification of asynchronous circuits by BDD-based model checking of Petri nets
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