Parallel assertions for architectures with weak memory models

DOI10.1007/978-3-642-33386-6_21zbMATH Open1374.68106OpenAlexW1894736207WikidataQ62040451 ScholiaQ62040451MaRDI QIDQ4649301FDOQ4649301

Authors: Daniel Schwartz-Narbonne, Georg Weissenbacher, Sharad Malik 

Publication date: 21 November 2012

Published in: Automated Technology for Verification and Analysis (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-33386-6_21

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Mathematics Subject Classification ID

Other programming paradigms (object-oriented, sequential, concurrent, automatic, etc.) (68N19) Semantics in the theory of computing (68Q55)

Cited In (2)

• Underspecified harnesses and interleaved bugs
• The impact of memory models on software reliability in multiprocessors

Uses Software

• LLVM
• PARSEC

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