scientific article; zbMATH DE number 1909483
From MaRDI portal
Publication:4805355
zbMATH Open1025.94026MaRDI QIDQ4805355FDOQ4805355
Authors: Nicola Nicolici, Bashir M. Al-Hashimi
Publication date: 13 May 2003
Title of this publication is not available (Why is that?)
Recommendations
- Test schedules for VLSI circuits having built-in test hardware
- scientific article; zbMATH DE number 1380625
- Sequential test generators: past, present and future
- A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS
- scientific article; zbMATH DE number 964559
Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)
Cited In (4)
- Test schedules for VLSI circuits having built-in test hardware
- The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications
- Energy saving testing of circuits
- NBTI and power reduction using an input vector control and supply voltage assignment method
This page was built for publication:
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4805355)