A pipelined multi-core MIPS machine. Hardware implementation and correctness proof

DOI10.1007/978-3-319-13906-7zbMATH Open1304.68005OpenAlexW2493981662MaRDI QIDQ481104FDOQ481104

Authors: Yong-Cai Geng, Sumit K. Garg 

Publication date: 12 December 2014

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-319-13906-7

Recommendations

• Modular deductive verification of multiprocessor hardware designs
• Formal verification of a complex pipelined processor
• scientific article; zbMATH DE number 53982
• Correct Hardware Design and Verification Methods
• The notion of proof in hardware verification

zbMATH Keywords

multi-corehardware implementationcorrectness proofMIPS

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to computer science (68-02) Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30) Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

Cited In (4)

• Title not available (Why is that?)
• Synthesizing and verifying multicore parallelism in categories of nested code graphs
• Modular deductive verification of multiprocessor hardware designs
• Mothers of pipelines

This page was built for publication: A pipelined multi-core MIPS machine. Hardware implementation and correctness proof

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q481104)