scientific article; zbMATH DE number 1400095
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(6)- Verification of FPGA layout generators in higher-order logic
- Correct Hardware Design and Verification Methods
- Theorem Proving in Higher Order Logics
- Automatic analysis of DMA races using model checking and \(k\)-induction
- Formally analyzed dynamic synthesis of hardware
- scientific article; zbMATH DE number 1844671 (Why is no real title available?)
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