A 6-to-10-Bit 0.5 V-to-0.9 V Reconfigurable 2 MS/s Power Scalable SAR ADC in 0.18 <formula formulatype="inline"> <tex Notation="TeX">\mu{\rm m}</tex></formula> CMOS

DOI10.1109/TCSI.2014.2377431MaRDI QIDQ5007672zbMATH OpenFDO

Authors Zhangming Zhu, Zheng Qiu, Maliang Liu, Ruixue Ding

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TCSI.2014.2377431

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Cited in

(1)

• An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS

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