High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
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Publication:5007819
DOI10.1109/TCSI.2015.2403032zbMath1468.94430OpenAlexW2075568400MaRDI QIDQ5007819
Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy Paily
Publication date: 26 August 2021
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tcsi.2015.2403032
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