A VLSI Efficient Programmable Power-of-Two Scaler for \{2ⁿ-1,2ⁿ,2ⁿ+1\} RNS

DOI10.1109/TCSI.2012.2206491MaRDI QIDQ5010496zbMATH OpenFDO

Authors Jeremy Yung Shern Low, Chip-Hong Chang

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TCSI.2012.2206491

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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