Synthesis for testability: Binary Decision Diagrams

DOI10.1007/3-540-55210-3_208zbMath1494.94059OpenAlexW2966097595MaRDI QIDQ5096806

Bernd Becker

Publication date: 18 August 2022

Published in: STACS 92 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/3-540-55210-3_208

zbMATH Keywords

synthesistestabilityVLSI structuresfault model

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Switching theory, applications of Boolean algebras to circuits and networks (94C11)

Uses Software

• ROBDD

Cites Work

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• Modified branching programs and their computational power
• Graph-Based Algorithms for Boolean Function Manipulation
• Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits
• Binary Decision Diagrams

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