High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

DOI10.1109/TC.2019.2957355OpenAlexW2992628949MaRDI QIDQ5125896

Sumio Morioka, Jean-Luc Danger, Yves Mathieu, Naofumi Homma, Tarik Graba, Makoto Nagata, Kohei Matsuda, Noriyuki Miura, Shivam Bhasin, Rei Ueno

Publication date: 2 October 2020

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2019.2957355

Mathematics Subject Classification ID

Computer science (68-XX)

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