Relaxed memory models
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Publication:5261535
DOI10.1145/1480881.1480930zbMATH Open1315.68173OpenAlexW2104245532MaRDI QIDQ5261535FDOQ5261535
Publication date: 3 July 2015
Published in: Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1145/1480881.1480930
Cited In (16)
- Title not available (Why is that?)
- Operational semantics of a weak memory model with channel synchronization
- A denotational semantics for SPARC TSO
- Operational semantics of a weak memory model with channel synchronization
- Parallelized sequential composition and hardware weak memory models
- An Isabelle/HOL formalisation of the SPARC instruction set architecture and the TSO memory model
- Verification of STM on relaxed memory models
- Operational semantics with semicommutations
- Advances in Computer Science - ASIAN 2004. Higher-Level Decision Making
- Context-Bounded Analysis of TSO Systems
- Studying Operational Models of Relaxed Concurrency
- Observation-Based Concurrent Program Logic for Relaxed Memory Consistency Models
- A formal hierarchy of weak memory models
- Verified Software Toolchain
- Overcoming memory weakness with unified fairness. Systematic verification of liveness in weak memory models
- An operational happens-before memory model
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