The Time Dilation Technique for Timing Error Tolerance
From MaRDI portal
Publication:5268212
Recommendations
- Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience
- Timing Error Tolerance in Small Core Designs for SoC Applications
- scientific article; zbMATH DE number 4043219
- Orthogonal accuracy clock synchronization
- Error Analysis and Bounds in Time Delay Estimation
- Dynamic fault-tolerant clock synchronization
Cited in
(5)
This page was built for publication: The Time Dilation Technique for Timing Error Tolerance
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5268212)