High-Speed Architectures for Multiplication Using Reordered Normal Basis

DOI10.1109/TC.2010.218zbMATH Open1365.65314MaRDI QIDQ5277656FDOQ5277656

Authors: Ashkan Hosseinzadeh Namin, Huapeng Wu, M. Ahmadi 

Publication date: 12 July 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04)

Cited In (1)

• A survey of some recent bit-parallel \(\mathrm{GF}(2^n)\) multipliers

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