Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache

DOI10.1109/TC.2010.203zbMATH Open1368.68091MaRDI QIDQ5280642FDOQ5280642

Authors: Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia 

Publication date: 27 July 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited In (4)

• Test Algorithms for ECC-Based Memory Repair in Ultimate CMOS and Post-CMOS
• Smart ECC Allocation Cache Utilizing Cache Data Space
• Dependability Aspects Regarding the Cache Level of a Memory Hierarchy using Hamming Codes
• On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

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