Improved Design of High-Performance Parallel Decimal Multipliers

DOI10.1109/TC.2009.167MaRDI QIDQ5280770zbMATH OpenOpenAlexWikidataFDO

Authors Álvaro Vázquez, P. Montuschi, Elisardo Antelo

Publication date 27 July 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2009.167

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04) Parallel numerical computation (65Y05)

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• Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers

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