CMOS Implementation of Nonlinear Spectral-Line Timing Recovery in Digital Data-Communication Systems

DOI10.1109/TCSI.2003.822395zbMATH Open1371.94012OpenAlexW2137578705MaRDI QIDQ5362906FDOQ5362906

Authors: Un-Ku Moon, Gang Huang 

Publication date: 4 October 2017

Published in: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2003.822395

Mathematics Subject Classification ID

Communication theory (94A05)

Cited In (2)

• A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process
• Analysis and design of timing recovery schemes for DMT systems over indoor power-line channels

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