Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors

DOI10.1109/TC.2017.2779480zbMATH Open1395.68074OpenAlexW2774506405MaRDI QIDQ5375290FDOQ5375290

Authors: Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout 

Publication date: 14 September 2018

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.2017.2779480

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited In (1)

• On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

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