Bit-serial systolic divider and multiplier for finite fields GF(2/sup m/)

DOI10.1109/12.156540zbMATH Open1397.65331OpenAlexW2099711671MaRDI QIDQ5375359FDOQ5375359

Authors: Vijay K. Bhargava, M. Anwar Hasan 

Publication date: 14 September 2018

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.156540

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

Cited In (5)

• A survey of some recent bit-parallel \(\mathrm{GF}(2^n)\) multipliers
• Hardware implementation of finite-field division
• Computational Science and Its Applications – ICCSA 2004
• A dual basis bit-serial systolic multiplier for GF(2 )
• A new bit-serial multiplier over \(GF(pm)\) using irreducible trinomials

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