Fast parallel algorithms for binary multiplication and their implementation on systolic architectures

DOI10.1109/12.21128MaRDI QIDQ5375462zbMATH OpenOpenAlexFDO

Authors Bhabani P. Sinha, Pradip K. Srimani

Publication date 14 September 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.21128

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04) Parallel numerical computation (65Y05) Analysis of algorithms and problem complexity (68Q25)

Cited in

(6)

• Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems
• Efficient Parallel Evaluation of Straight-Line Code and Arithmetic Circuits
• scientific article; zbMATH DE number 1223727 (Why is no real title available?)
• scientific article; zbMATH DE number 1057763 (Why is no real title available?)
• scientific article; zbMATH DE number 1405674 (Why is no real title available?)
• Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials

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