A study of two approaches for reconfiguring fault-tolerant systolic arrays

DOI10.1109/12.24292MaRDI QIDQ5375478zbMATH OpenOpenAlexFDO

Authors Hon F. Li, R. Jayakumar, Clement Lam

Publication date 14 September 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.24292

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cited in

(3)

• A fault-tolerant hexagonal systolic array
• On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors
• A systematic approach for designing concurrent error-detecting systolic arrays using redundancy

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