AT/sup 2/-optimal Galois field multiplier for VLSI

DOI10.1109/12.29475zbMATH Open1395.68355OpenAlexW2085802456MaRDI QIDQ5375490FDOQ5375490

Authors: K. Mehlhorn, Martin Fürer 

Publication date: 14 September 2018

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/12.29475

Mathematics Subject Classification ID

Number-theoretic algorithms; complexity (11Y16) Numerical methods for discrete and fast Fourier transforms (65T50) Numerical algorithms for specific classes of architectures (65Y10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (1)

• A survey of some recent bit-parallel \(\mathrm{GF}(2^n)\) multipliers

This page was built for publication: AT/sup 2/-optimal Galois field multiplier for VLSI

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5375490)