On the Fault Testing for Reversible Circuits

DOI10.1007/978-3-540-77120-3_70zbMath1193.94088OpenAlexW1590527680MaRDI QIDQ5387815

Satoshi Tayu, Shigeru Ito, Shuichi Ueno

Publication date: 27 May 2008

Published in: Algorithms and Computation (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-77120-3_70

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Computational difficulty of problems (lower bounds, completeness, difficulty of approximation, etc.) (68Q17)

Cites Work

• Unnamed Item
• Logical Reversibility of Computation

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