Development of tests for VLSI circuit testability at the upper design levels

DOI10.1134/S0005117910090110MaRDI QIDQ544693zbMATH OpenOpenAlexFDO

Authors L. A. Zolotorevich, A. V. Il'inkova

Publication date 16 June 2011

Published in Automation and Remote Control (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1134/s0005117910090110

Mathematics Subject Classification ID

Applications of design theory to circuits and networks (94C30)

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Cites work

• Diagnosis of Automata Failures: A Calculus and a Method
• Polynomially Complete Fault Detection Problems
• Switch-level VLSI quasistatic simulation methods: comparative accuracy of models

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• Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models
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