scientific article; zbMATH DE number 5032602
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Publication:5472089
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(7)- Reliable synthesis of logic circuits
- Synthesis of delay-verifiable combinational circuits
- Algorithms for computing minimal equivalent subformulas
- A generalized if-then-else operator for the representation of multi-output functions
- On Tackling Explanation Redundancy in Decision Trees
- scientific article; zbMATH DE number 7561750 (Why is no real title available?)
- scientific article; zbMATH DE number 7301717 (Why is no real title available?)
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