Formal Methods in Computer-Aided Design

DOI10.1007/B102264zbMATH Open1117.68436OpenAlexW4229585471MaRDI QIDQ5492989FDOQ5492989

Authors: Marko Samer, Helmut Veith 

Publication date: 20 October 2006

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/b102264

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Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (12)

• Inherent vacuity in lattice automata
• Efficient detection of vacuity in temporal model checking
• Vacuity in Testing
• Formal Methods in Computer-Aided Design
• Vacuity in practice: temporal antecedent failure
• Before and after vacuity
• On the Notion of Vacuous Truth
• Synthesizing non-vacuous systems
• Computer Aided Verification
• Tools and Algorithms for the Construction and Analysis of Systems
• Vacuity in synthesis
• Beyond vacuity: towards the strongest passing formula

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