Fault Equivalence in Combinational Logic Networks

DOI10.1109/T-C.1971.223129zbMATH Open0231.94035OpenAlexW2043111827MaRDI QIDQ5639633FDOQ5639633

Authors: Edward J. McCluskey, Frederick W. Clegg 

Publication date: 1971

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/t-c.1971.223129

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cited In (4)

• Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices
• On the construction of hierarchic models
• Toward a definition of fault analysis for Petri nets models
• An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits

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