Ternary logic in parallel multipliers

DOI10.1093/COMJNL/15.3.254zbMATH Open0241.94039OpenAlexW2072836619MaRDI QIDQ5652565FDOQ5652565

Zvonko G. Vranesic, V. Carl Hamacher

Publication date: 1972

Published in: The Computer Journal (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1093/comjnl/15.3.254

Mathematics Subject Classification ID

Many-valued logic (03B50)

Cited In (1)

• A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders

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