A Proper Model for Testing the Planarity of Electrical Circuits

DOI10.1002/J.1538-7305.1973.TB03188.XzbMath0258.94019OpenAlexW1997880829MaRDI QIDQ5675628

D. G. Schweikert, A. J. Goldstein

Publication date: 1973

Published in: Bell System Technical Journal (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1002/j.1538-7305.1973.tb03188.x

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Applications of graph theory to circuits and networks (94C15)

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Orthogonal drawings of graphs for the automation of VLSI circuit design

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