FPGA prototyping of RNN decoder for convolutional codes

DOI10.1155/ASP/2006/15640MaRDI QIDQ5898702zbMATH OpenOpenAlexDBLPWikidataFDO

Authors Zoran Salcic, Stevan Berber, Paul Secker

Publication date 19 March 2007

Published in EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1155/asp/2006/15640

Mathematics Subject Classification ID

Decoding (94B35)

Review text

Summary: This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA), thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.

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• FPGA prototyping of RNN decoder for convolutional codes

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